The present invention generally relates to systems and methods for counting. Particularly, the invention relates to a simplified counter capable of supporting several different count schemes.
To achieve higher speed systems, manufacturers are producing more specialized electronic component parts. For example, central processing units (CPUs) are being designed for use in conjunction with either linear-burst or interleaved-burst memory systems. In a linear-burst system, memory addresses are accessed in a sequential order. In contrast, an interleaved-burst memory system addresses memory in a non-sequential, or interleaved fashion.
Memory manufacturers, on the other hand, have continued to develop memory systems which function only in conjunction with interleaved-burst CPUs or which function only in conjunction with linear-burst CPUs. This approach is undesirable for several reasons. First, it requires that memory system manufacturers design, produce, fabricate, and assemble different designs and layouts for two relatively similar memory systems. It also forces manufacturers to maintain different inventories and supply channels for those components, thereby increasing the overall cost and overhead associated with each component.
One solution to this problem would be to integrate circuitry for interleaved counts and circuitry for sequential counts onto each memory component. This solution, however, is also undesirable as the additional unused circuitry would occupy valuable substrate and lead space which could otherwise be used to increase memory capacity or capability.
There is, therefore, a need for a single counter system which accommodates both interleaved and sequential count schemes.